Yiğit Keleş
@AdelestonStudying in Gazi University Technology Faculty Computer Engineering ,nowadays
3
Followers
5
Following
15
Public Repos
0
Private Repos
Language Breakdown
Lines of code distribution across 14 owned repositories
327.7M
Total LOC
Verilog
276,928,169 lines
84.5%
N/A
C
35,558,708 lines
10.8%
N/A
C++
10,297,708 lines
3.1%
N/A
Python
2,348,785 lines
0.7%
N/A
Tcl
1,655,505 lines
0.5%
N/A
Other
952,710 lines
0.3%
N/A
I
I-Shaped Developer
I-shapedSpecialist — deep expertise in Verilog
Verilog
C
C++
Python
Tcl
Collaboration Network
Global Impact visualization
Repos
17
PRs
0
Growth
+18%
Top Collaborators
No collaborator data yet.
Coding Streak
Contribution activity over the past year
1 day
11
Contributions
10
Commits
0
Pull Requests
Jun
Jul
Aug
Sep
Oct
Nov
Dec
Jan
Feb
Mar
Apr
May
Jun
Mo
We
Fr
Based on GitHub activity
Less
More
Following
5 total
PEYMAN
@Peymanc1
Cra2yPierr0t
@Cra2yPierr0t
veliCosanay
@veliCosanay
Sal Zhang
@salzhang
Sener Dag
@senerdag
Synced via GitHub
Top Repositories
RiscV32iExperience
preliminary for Teknofest Digital Processor Contest
1
0
Verilog
CFU-PlaygroundInternship
0
0
C
Caravel_User_Project_via_Encoder_ip-tools
0
0
SoC_Yongatek_kremali
0
0
Verilog
caravel_SoC_framework
0
0
Verilog
YongaTekCaravelSoCCalismasi
0
0
Verilog
caravel-mpw9-test
Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.
0
0
Verilog
Caravel-Test
0
0
Verilog
caravel_denemem
0
0
Verilog
ChipCommunicationModulesRtl
0
0
Verilog
Open Source Impact
Contributions to external projects
0 merged PRs
No external contributions found.